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16E1 EOPDH Converter (RC6116)

RC6116 is a highly integrated device implements Ethernet frame transmission over 1~16 E1 links. Compliant to international standards, the device can communicate with products from other manufacturers adopting the same standards.
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    RC6116 is a highly integrated device implements Ethernet frame transmission over 1~16/5 E1 links. Compliant to international standards, the device can communicate with products from other manufacturers adopting the same standards.


    • Capability of inverse multiplexing from one MII to 1-16/5 E1s
    •  The maximum tolerated differential delay is 220ms
    •  Ethernet Interface
    •  Compliant with IEEE 802.3
    •  100M Full-duplex mode
    •  Configurable PAUSE flow control
    •  Maximum frame size of 2036 bytes
    •  For PHY mode, an external Ethernet switch chip is required
    •  Encapsulation
    •  Compliant with GFP-F Encapsulation specified in ITU-T G.7041
    •  Programmable Null/ Linear header and optional FCS check for encapsulation
    •  Auto-adaptive Client Data/ Client Management Frame, Null/ Linear extension header and FCS/ no FCS for decapsulation
    •  Capability of LOF (Loss Of Frame) detection
    •  Provide frame statistic in framer and deframer
    •  Provide standard management frame
    •  Virtual Concatenation
    •  Compliant with VCAT and LCAS specified in ITU-T G.7042
    •  VCAT & LCAS mapping into E1 complies withITU-T G.7043, G.8040
    •  Differential delay detection
    •  Hitless bandwidth adjustments (combined with processor)
    •  Automatic removal and recovery of E1 channels when urgent alarm occur or disappear
    •  Automatic removal and recovery of E1 channels when high Bit Error occur or disappear (combined with processor)
    •  Support unbalanced bandwidth usage – when some E1s cannot work properly (i.e., the bandwidth of the transmitting and receiving signals can be 5 E1s and 3 E1s respectively)
    • E1 Interface
    •  Compliant with ITU-T G.703, G.704, G.823
    •  Programmable HDB3/ NRZ code for
    •  Alarm monitor and CRC error counter
    •  Provide transparent channel through SA bits for the communication between local and remote microprocessor
    •  Provide HDLC framer / deframer controlled by processor
    •  Programmable local / tracing E1 timing mode
    •  Per-port diagnostic line loopback
    •  Support embedded E1 BER Tester(BERT for statistic of bit errors )
    •  Non-multiplexed Intel Processor Interface
    •  Serial data input / output which is used for alarm LEDs and configuration controlled by register
    •  External 4Mbits×16 (64Mbits) SDRAM 
    •  QFP 208 Package, 3.3V/1.8V power supply
    •  fully compatible pins for RC6116/RC6105

    Functional Block Diagram


    Figure 1 Functional Block Diagram




    Figure 2 Application


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