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Multi-functional Ethernet converter (RC7222A2)
The RC7222A2 is a highly integrated ASIC chip for data conversion from 10M/100M Ethernet and ST_BUS to WAN interfaces (E1/FE1, or SSI*). It supports E1/FE1 and MII interfaces that follow ITU-T standards.
Complying with ITU-T G.7041, or being compatible with RJ017*, GFP-F and HDLC can be selected to encapsulate Ethernet frames. It supports Client Management Frame (CMF) not only for GFP, but also for HDLC. Furthermore, for HDLC encapsulation, RC7222A2 defines a particular CMF data format which meets most of requirements for in-band remote monitoring. Additionally, making use of the reserved bit (SA) of G.704, RC7222A2 sets up an independent channel for low speed remote monitoring.
Inside the chip, when Ethernet data are cached, encapsulated and counted, it is monitored in every step, and all of the alarms and statistic result can be read from the registers.
MP interface is designed to view the working status and configure the chip. For CPU less application, most of the functions can be configured by means of its pins.
1) ‘SSI’ stands for Serial Synchronous Interface. It’s a HDLC interface, as a matter of fact.
2) RJ017 is an Ethernet bridge chip produced by RAD Data Communications, Israel.
- Ethernet Interface
- The MII (Media Independent Interface) supports 10M/100M, Full/Half-duplex modes, completely compatible with the IEEE 802.3
- The length of transportable Ethernet frames ranges from 64 to 2031 bytes
- Discards the oversized, undersized and CRC error packets
- Supports PAUSE flow control function
- Provides Ethernet alarm report test and performance statistics
- Provides MDIO interface to realize registers’ mapping from Ethernet PHY to the RC7222A2.
- E1/FE1 Interface
- E1 interface conforms to the ITU-T G.703, G.704, G.706 and G.732 recommendations
- HDB3 and NRZ are selectable
- Local free running or tracking line timing can be selected
- SSI Interface
- With slaved timing mode, transmits and receives HDLC data stream, and the bit rate can be up to 50Mbit/s
- The Ethernet frame coming from the MII interface is encapsulated first by built in HDLC framer
- G.704 Framer
- Supports G.704 framer/de-framer by-pass mode (un-framed)
- Supports PCM30/31 mode
- Supports CRC-4 multiframe auto-adaption
- The reserved SA bits can be used as a 20Kb/s
- transparent synchronous interface
- Ethernet Frame Encapsulation
- Supports HDLC compatible with RJ017
- Supports GFP-F complying with the ITU-T G.7041
- Supports CSF frames and detects alarm when receiving CSF
- The parameters PTI/PFI/EXI are auto-adaptive at the receiving side with powerful compatibility
- Client Management Frame (CMF)
- For HDLC encapsulation, the RC7222A2 supports CMF complying with China Mobile format, and optionally, user defined CMF is also possible
- For GFP encapsulation, supports user defined CMF
- Connecteded externally with 64Mbit SDRAM; Cache capacity : 32--512 frames(selectable)
- Supports 19200bps UART interface or 100kb/s I2C interface
- For UART control, supports address oriented management, and maximum number of controlled objects can be 256 at most
- The status of RC7222A2 and the Ethernet PHY at the remote can be monitored in G.704 framing mode
- Supports user-defined information between the local and Remote via SA bit channel in the G.704 framing mode
- Provides chip soft-reset register
- Relying on internal second timer, performance statistics records can be reported every second
- Supports local and remote loop back and the built-in BERT as well
- The anti-loopback function prevents the Ethernet network from breakdown when a line Loop back occurs
- 0.25μm CMOS; 2.5V and 3.3V power; LQFP128 package
Functional Block Diagram
Figure RC7222A2 Functional Block Diagram
- Ethernet to E1 Converter
RC7222A2 can be used in data conversion from Ethernet to single E1.
Figure 1 The Block Diagram for Ethernet to E1 Converter
- SSI Application
Working together with other line interface chips, the RC7222A2 can realize the multiplexing for Ethernet, voice and
other services to optic / E1 signals, based on 64Kb/s.
Figure 2 The Block Diagram for a SSI Application