Monolithic SDH ADM Multiplexe (RC7880A1)

Overview

RC7880A1 is a monolithic SDH Add/Drop multiplexer which multiplexes 24 E1s to dual STM-1 optical line interfaces. With a few external components, the STM-1 ADM equipment can be realized. RC7880A1 can be used as a Customer Premises Equipment (CPE), an Add-Drop-Multiplexer (ADM) or Multi-Service Access platform equipment (MSAP) to build various transmission networks.

RC7880A1 complies with ITU-T G.707/ G.781/ G.783/ G.813/ G.703/ G.704/ G.664 series recommendations. It adopts RPD and AIS+ patented technology developed by RAYCOM Technology.

Features

•  Realize STM-1 ADM optical transmission system on monolithic chip
•  Supports dual STM-1 line interfaces for ADM/TM application.
•  24 E1 asynchronous mapping/de-mapping.
•  External synchronous equipment clock interface.
•  Overhead interface and EOW unit.
•  TU-12/TU-3 space division cross-connect.
•  Supports 64Kb/s based overhead cross-connect.
•  Dual Simplified Telecom-bus interfaces for E1/E3/Ethernet service extension
•  Supports hardware based SNC/I and SNC/N protection.
•  Supports dual G.704 E1 framers achieving XE1 interfaces that carry selected SOH overhead bytes (such as D1~D12/E1/E2/F1) and can be directly mapped into STM-1 optical ports as amanagement tunnel passing through the existing SDH networks.
•  Embedded E1 BERT, with PRBS generato/detector for offline testing, and G.704 CRC-4 detector for online testing.
•  LOHP Unit
•  Dual units for STM-1 line overhead process.
•  Optical A/B interfaces can be set as TU-12 or TU-3 or VC-4 structure independently.
•  Built-in 155.52Mb/s CDR, provide LVDS TX&RX interfaces.
•  AU-4 pointer process.
•  RSOH/MSOH/VC-4POH overhead process.
•  Monitors OOF, LOF, LOM, MS-AIS, AU-LOP, AU-AIS.
•  Monitors bit or block errors of B1, B2, B3, M1, G1 overhead.
•  Supports J0(1/16Bytes), J1(16Bytes) trace identifier.
•  Supports Automatic Laser Shutdown (ALS).
•  Supports Remote Power down Detect (RPD).
•  Supports outward and inward loop back of line signal at the point of 155M input/output ports.
•  Needs a 19.44MHz±20ppm reference clock for CDR.
•  MAPPING Unit
•  Supports 24 E1 mapping /de-mapping asynchronously to/from internal Telecom-bus.
•  Supports STB_G/STB_H dual simplified Telecom buses.
•  Supports both path protection and non-protection configuration, and sectional E1 connection is possible when non-protection selected.
•  Processes TU-12 pointer, TU12- LOP and TU12-AIS alarm are monitored.
•  Processes V5, J2 (16 bytes), N2, K4 overhead.
•  Processes BIP-2, REI and RDI of V5 byte overhead.
•  Provides a 32 bits (4-byte register) low bit rate communication tunnel for each E1 using the O-BIT (or N2 byte) overhead.
•  The time slots of STB-G bus and STB-H bus within the range from #0 to #62 can be flexibly assigned to each E1.
•  Hardware based protection facility achieves recovering time less than 50ms.
•  Protection switch can be triggered by alarm of TU-12 pointer and VC-12 channel depending on the configuration.
•  Supports both HDB3 and NRZ code type. Built-in E1 clock and data recovery allows simplified LIU employed.
•  Supports HDB3 code violation (CV) detection, one clear-after-read CV detection register for each E1.
•  Supports E1 inward and outward loop back (and AIS is optionally inserted into downstream when E1 loop back is enabled).
•  Support AIS+, a special coded AIS signal.
•  STBI Unit
•  Dual 38.88MHz simplified telecom bus interfaces for E1/E3/Ethernet service extension.
•  Supports TU-12/TU-3 format with fixed multi-frame alignment
•  TUPP Unit
•  For at most 126 TU-12s or at most 6 TU-3s structure
•  Support mixed-structure of TU-12 and TU-3
•  Monitor TU12-LOP, TU12-AIS, TU3-LOP and TU3-AIS alarm
•  TU-DXC Unit
•  252X252 TU-12 space division switching matrix
•  12X12 TU-3 space division switching matrix
•  Supports two kinds of connection modes: add/drop and passing through.
•  Monitors TU-12/TU-3 pointer status for SNC/I protection
•  Supports TU-12/TU-3/VC-4 signal loop back toward to optical ports.
•  SEC unit
•  Achieves good quality of Synchronous Equipment Clock(SEC) making use of internal DPLL and external VCXO with output frequency of 155.52MHz, 38.88MHz, 8.192MHz and 2.048MHz.
•  Connects external VCXO with the LVDS interface.
•  Needs a high accurate 65.537MHz oscillator that determines the quality of SEC in free running mode.
•  The default bandwidth of the DPLL is 9Hz.
•  The timing sources can be four T1, one T2 or two T3 references.
•  T2 reference can be selected from any of 24 E1 input signals.
•  T3 reference can be 2.048MHz or 2.048Mb/s.
•  T4 reference outputs can be 2.048MHz or 2.048Mb/s.
•  Supports SSM for T1, T2, T3 and T4 references.
•  Supports three working modes: tracing, hold over and free running.
•  Complies with ITU-T G.783 and ITU-T G.813 recommendation
•  OHI Unit
•  Provides two 192Kb/s (576Kb/s) DCC interfaces for connecting external HDLC controller.
•  Provides F1 or F2 overhead channels by asynchronous sampling clock at 64 KHz.
•  Integrates two E1 interfaces (XE1) carrying E1/E2/F1/D1-D12 overhead bytes to support E1 based network management extension.
•  Supports 8.192 Mb/s overhead bus SO8M, for overhead connection among several chips within one equipment
•  OH-DXC Unit
•  Supports 64Kb/s based 256×256 non-blocking cross-connects to enable E1/E2/F1/F2/F3/D1~D12 overhead bytes to be switched among the two STM-1 interfaces and other OHI interfaces.
•  EOW Unit
•  Utilizes a 2.048Mb/s PCM-bus to directly connect to a CODEC device (A-law PCM coding).
•  Needs an external DTMF detector.
•  The address oriented engineering order wire is realized based on the private signaling system and the hardware switching facility. Do not need software intervention.
•  Supports Dial-up service
•  E1 or E2 overhead bytes can be selectable.
•  Provides four tone generators: dialing, ringing back and busy and howling.
•  GSIO Unit
•  GSIO consists of 2.048MHz clock, 8000Hz frame alignment signal, serial data input and serial data output.
•  GSIO is directly connected to external 74LS165 / 74LS595 devices.
•  Maximum capability is 32 bits for input and output respectively.
•  BERT Unit
•  Achieves built-in E1 bit Error Tester
•  Built-in a 2.048Mb/s, 2E15-1 pseudo random bit sequence (PRBS) generator and detector.
•  Built-in a G.704 de-framing unit for online CRC-4 monitoring
•  Supports single bit error insertion.
•  Provides E1-AIS/E1-LOS/E1-LOF alarm.
•  Provides CRC-4/PBRS15/CV bit error counters
•  MPI Unit
•  Intel compatible 8 bits non-multiplexed processor interface.
•  Interrupt signal is not provided.
•  Provides register writing protection lock.
•  Technology Process
•  All input buffers are 5V compatible except for MP data bus and LVDS inputs.
•  3.3V , 2.5V and 1.5V power supply
•  Maximum power consumption is less than 1.0W.
•  LQFP256 lead-free package with 0.4mm pitch of pins.

Functional Block Diagram

Figure  RC7880A1 Block Diagram

Application

• SDH ADM/TM Multiplexer
• SDH Customer Premises Equipment (CPE)
•  MSAP Multi-service Access Platform Equipment

Figure 1 RC7880A1 ADM Application